|
Coffee Break
10:30 - 11:00 am
Lunch
12:30 - 1:30 pm
Coffee Break
3:00 - 3:30 pm |
Defect-aware to Power-conscious
Tests : The New DFT Landscape
Janusz Rajski & Nilanjan Mukherjee
Mentor Graphics, and Jerzy Tyszer
Poznan Univ |
Techniques for the Design of Low
voltage Power Efficient Analog and
Mixed-signal Circuits, Jamie
Ramirez-Angulo New Mexico State Univ,
Ramon Carvajal Univ de Sevilla, &
Antonio Lopez-Martin Univ. de
Navarra
Presented By
Shouri Chatterjee, IIT Delhi,
Prakash Easwaran & C. Srinivasan,
Cosmic Circuits |
Power Reduction Techniques and
Flows and RTL and System Level
Anmol Mathur Calypto, Qi Wang
Cadence, & Vani Dimri, Virage Logic |
Security & Dependability of
Embedded Systems: A Computer
Architect's Perspective
Sri Parmeswaran & Roshan Ragel
Univ of NSW, Joerg Henkel Univ of
Karlsruhe, & V. Narayanan Penn State |
|
Coffee Break
10:30 - 11:00 am
Lunch
12:30 - 1:30 pm
Coffee Break
3:00 - 3:30 pm |
Design for Manufacturability and
Reliability in Nano Era Goutam
Debnath & Paul Thadikaran Intel |
Negative Feedback System and
Circuit Design
Nagendra Krishnapura & Shanthi Pavan
IIT Madras |
Synthesis & Testing for Low Power
Ajit Pal & Santanu Chattopadhyay IIT
Kharagpur |
Robust Circuit Design: Challenges
and Solutions
Saurabh Tiwary Cadence, Amit Singhee
IBM & Vikas Chandra ARM |
