A Decade of Platform-Based Design:    A look backwards,
a look forwards

Grant Martin,  Chief Scientist, Tensilica

Abstract:

It has been 10 years since a group of us wrote the book "Surviving the SoC Revolution: A Guide to Platform-Based Design", and almost a decade since I gave a talk at VLSI 2000 in Kolkata about this theme. The intervening time has seen considerable development in the platform based design approach.  It has become the near ubiquitous approach to the development of complex SoCs for many application areas.   It has branched out from its original, mainly hardware-centric focus, to assume much more of a system and software focus complementing hardware.  And the nature of platform architectures have changed:   we now see many more embedded processors of all kinds in SoC platforms, from  application-specific processors (ASIPs) to clusters of homogeneous or heterogeneous processing engines and many integrated subsystems each including one or more ASIPs or general purpose cores.

This talk will look back at the past decade in platform based design and describe the evolution of architectures, design approaches and tools, and also look forward at the next decade or two and try to paint some possible scenarios for the future evolution of the platform-based approach.    As we move towards new generations of design tools and higher level design approaches, what will be the main forms of platforms in future and how will designers use them?
 
Speaker Bio:

Grant Martin is a Chief Scientist at Tensilica, Inc. in Santa Clara, California. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/BNR in Canada for 10 years;  and Cadence Design Systems for 9 years, eventually becoming a Cadence Fellow in their Labs.   He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation) from the University of Waterloo, Canada, in 1977 and 1978.

Grant is a co-author or co-editor of nine books dealing with SoC design, SystemC, UML, modelling, EDA for integrated circuits and system-level design, including the first book on SoC design published in Russian.  His most recent book, “ESL Design and Verification”, written with Brian Bailey and Andrew Piziali, was published by Elsevier Morgan Kaufmann in February, 2007.

He was co-chair of the DAC Technical Program Committee for Methods for 2005 and 2006. His particular areas of interest include system-level design, IP-based design of system-on-chip, platform-based design, and embedded software. Grant is a Senior Member of the IEEE.
 

Analog IC Design in Nanometer CMOS Technologies

Prof. Willy Sansen, K.U. Leuven Belgium

Abstract:

In nanometer CMOS technologies, several new effects emerge, such as velocity saturation and gate leakage currents. As a result the transconductance and speed are both limited by velocity saturation. Also noise and mismatch are affected as a result of the thinner gate oxides used. Moreover the supply voltage is reduced to values below 1 Volt, creating new challenges for analog circuit design.

This presentation provides a review of the modifications in model parameters, including noise and distortion. It is followed by an exploration of the noise/power compromise in existing circuit blocks such as Miller operational amplifiers and Gm-C filters. An overview is the given of low-voltage amplifiers/filters configurations with both Gate and Bulk drives. Several sub-1 Volt circuits are finally discussed for different applications.

Speaker Bio:

Prof. Willy Sansen has the PhD degree from the University of California, Berkeley in 1972. Since 1980 he has been full professor at the Catholic University of Leuven, in Belgium, where he has headed the ESAT-MICAS laboratory on analog design since 1984. He has been supervisor of sixtyfive PhD theses and has authored and coauthored more than 625 publications and sixteen books, among which "Analog Design Essentials". He is a Fellow of the IEEE. He was program chair of the ISSCC-2002 conference and is now President of the IEEE SSCS.

DFX and Productivity

Dr. Robert C Aitken, R&D Fellow, ARM

Abstract:

CMOS scaling has led to ever-increasing numbers of potentially available transistors on chips. At the same time, design productivity has also continued to improve, but has not been able to keep up, resulting in increasing design effort. Many factors contribute to this situation, but one key element is the complexity involved in ensuring that yield targets will be met. (DFY). This talk outlines the basics of design-for-yield (DFY) and shows how it relates to design-for-manufacturability, test, and variability (DFM, DFT, and DFV respectively). It is shown how a comprehensive approach to all of the problems, known as DFX, can lead to improved design methodology and hence improved productivity.

 

Speaker Bio:

Robert C. Aitken is an R&D Fellow at ARM. His areas of responsibility include low power design, library architecture, and design for manufacturability. He has worked on design, manufacturing and variability issues for many years at ARM, Artisan, Agilent and HP. He has given tutorials and short courses on a variety of subjects at conferences and universities worldwide. He has published over 70 technical papers, and holds a Ph.D. degree from McGill University in Canada.
 

Common Power Format: A User-driven Ecosystem
For Proven Low Power Design Flows

Dr. Sumit DasGupta, Senior Vice President, Si2

Abstract:

Low power design has emerged as one of the urgent needs in IC design. The International Technology Roadmap for Semiconductors (ITRS) has identified the challenges surrounding low power design as one of the fundamental bottlenecks in exploiting the full capabilities of some of the advanced technology nodes. In fact, data from major chip design houses have underscored this need.

Much attention has been focused world-wide on the three existing formats for expressing low power constraints and intent: Common Power Format (CPF) from Silicon Integration Initiative (Si2), UPF 1.0 from Accellera, and UPF 2.0/P1801 from IEEE. However, the real challenge lies in the development of design flows and tools that exploit the content expressed by designers in these formats to solve real-life, power-related issues in design. Therefore, it should come as no surprise that at Si2 the focus has been on both developing and standardizing CPF in a coalition of both users and EDA suppliers, and in creating an ecosystem that provides training and adoption aids for CPF to support its adoption by chip designers and tool developers alike and proliferation of CPF into design flows in IC companies around the world.

This presentation begins with a brief introduction on Si2 and the Low Power Coalition (LPC) and the processes used in LPC to drive the development of CPF. There will be a discussion on the CPF roadmap with an introduction of the current standard CPF version 1.1 identifying the key enhancements over the previous version 1.0, and the roadmap leading to version 1.2 where interoperability with P1801 is one of the focus items. Next, we will describe some of the enablers provided by Si2 to support adoption, such as, training materials, a parser, a reference guide and a relational analyzer which can be used both to train in CPF as well as to analyze the contents of multiple CPF files used across the design. The talk will include examples of adoption by EDA companies and will conclude with results achieved to-date among IC design companies with references to some real-life success stories in low power design.

Speaker Bio:

Sumit DasGupta is the Senior Vice-President of Engineering at Silicon Integration Initiative (Si2) an electronics industry consortium based in Austin, TX. Prior to joining Si2, Sumit was at Motorola Semiconductors, now Freescale, where he served as Director of Design Systems and was responsible for developing and integrating tools for the design of PowerPC microprocessors and SoC designs. Before Motorola, Sumit was at IBM where he served in senior management and technical leadership positions in the EDA field and was responsible for developing design tools and methods for physical design, and design for test, many of which are still in use today. Sumit has a PhD in Computer Science from Syracuse University. He has 8 patents issued and over 25 papers and publications. He is a Senior Member of the IEEE and has served in several leadership positions in IEEE events and activities.
 

The Future of Low Power Design is Here:  IEEE P1801, aka, UPF 2.0

Stephen Bailey, Director Product Marketing, Mentor Graphics

Abstract:

Industry adoption of Accellera’s Unified Power Format (UPF) has been broad and swift. And why shouldn’t it be?  For the first time, UPF made it possible to specify the power design intent in combination with the HDL specification of the design for use throughout the design, verification and implementation flows.  UPF’s portability and feature set opened the door for more efficient design of low power systems.  Now, UPF 2.0 is just around the corner.  The IEEE P1801 working group, by the time of this conference, will have completed the sequel and it will be well on its way to IEEE standardization.  Rumors are that there are significant changes to UPF 2.0.  Why has been UPF been enhanced?  What value will the new capabilities deliver?  Do the changes obsolete UPF 1.0?  This presentation will provide an overview of the major changes in UPF 2.0, its relationship with UPF 1.0 and the value that everyone doing low power designs will want to know.

Speaker Bio:

Stephen Bailey is Director of Product Marketing for Functional Verification at Mentor Graphics.  He has been active in EDA standards activities including chair of IEEE P1801 and Accellera UPF,  past chair of IEEE VHDL 1076 working group and participating in the PSL 1850 working group. He is the past technical program chair, vice chair and general chair for the DVCon Conference (2004-2008). With over 15 years of EDA and electronics industry experience, he has served in R&D, applications, consulting, and technical and product marketing roles.  Stephen has a BS and MS in Computer Science from Chapman University.
 

Making Sense Out of the Potential Babble of Low Power Standards

Dr. Gary Delp, Distinguished Engineer, LSI Corp

Abstract:

For decades designers have worked with the digital abstraction, signals are either logical true or logical false. As with all abstractions, this one had great utility, allowed optimizations in analysis, and separated two areas of difficult analysis, making the design task achievable. In 2009, this abstraction becomes more valuable, and more complex. Parts of digital circuits will be turned off relative to other parts, parts will enjoy low-power slow-down modes, and parts will scream with performance and energy. The good news is that there is a simple way to express the relationships, boundaries, activities, and side effects of many power domains without having to give up most of the simplifications that the digital abstraction allow us. The bad news is that there are currently two ways to do it.

Using examples from a number of design flows and design problems, the speaker will show how to use both UPF/P1801 and CPF to express the power constraints and characteristics of designs. As work is ongoing in both the Si2 Low Power Coalition, and the IEEE P1801 groups, the January state of interoperability will be greater than it is currently, and much quicker and cleaner to hear about than it has been to develop.

Speaker Bio:

Dr. Gary Delp is a Distinguished Engineer working out of the CTO office at LSI. As one of three architects of the Low Power Coalition, and vice-chair of the IEEE P1801 working group, he is in a unique position to provide insight into interoperability needs and potentials. Gary spends his time working on design and IP reuse, inside of a design, across designs, and across the economic eco-system. Some of this reuse is in the form of bundles and IP functions, some is in the form of formats, methodologies, and exploratory work. Standards Setting bodies, Industry Alliances and University research programs support this work of technology transfer.

He is the Technical Director of The SPIRIT Consortium, and the CTO of the VSI Alliance. He is also the vice-chair of the IEEE study group on common power formats. LSI has a keen interest in power reduction in service of the needs of their customers in the storage and consumer industries.

His work has always been in the area of system optimization, but the systems have varied. As a VLSI Designer at the IBM AS/400 Division, he led teams in the optimization of hardware/software tradeoffs for network interconnect and the provision of network services. He holds patents in scheduling and shaping algorithms, circuit design, chip product structures, and video editing among others. He works collaboratively; the bulk of his 40+ patents are joint with others. At the University of Delaware, his PhD. Dissertation was MemNet: a distributed shared memory network implementation and architecture. IBM Watson work included FDDI and ATM operating system/hardware interfaces.

He holds a Bachelor of Arts degree in Theatre from Oberlin College and a Master of Fine Arts in Technical Theatre from the University of Memphis, Tennessee. Delp received his PhD in Electrical Engineering from the University of Delaware and has taught in several institutions of higher education including Rhode Island College, Memphis State University, and the University of Delaware. Once, as technical director, he led a team in building 2 mountains for an outdoor historical drama in Chillicothe, Ohio.
 

Computational Lithography - Moore Bang for your Buck

Dr. Vivek Singh, Intel Fellow, Director of Computational Lithography Group

Abstract:

There have been many pronouncements about the slowing down of Moore's Law. Human enterprise, however, has managed to disprove these dim prophecies by producing ingenious solutions on a regular basis, to allow Moore's Law to continue its unabated march. Many of these solutions are coming from the growing field of Computational Lithography. Generally speaking, Computational Lithography comprises a broad set of techniques that use physics-based calculations to eke out more lithographic performance from today's steppers than they were originally designed for. Given the extraordinary cost of lithography tools and the fact that economics drives Moore's Law as much as physics, this boost in IC affordability is a key driver of innovations in Computational Lithography.

One such innovation is Pixelated Phase Mask technology. This technology was created to address the problem caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction was introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of techniques to maintain image quality. We sought to alleviate this problem by introducing additional degrees of freedom within the mask. The resulting Pixelated Phase Mask technology will be described in this paper, as an example of how Computational Lithography can contribute to affordable scaling and design productivity.

Speaker Bio:

Vivek Singh obtained his Ph.D. in 1993 from Stanford University, where he worked on simulations and experiments in plasma etching and deposition. He joined the TCAD department at Intel, where he worked on many different aspects of lithography technology development and optimization. Currently, he is a Senior Principal Engineer, and the Manager of Computational Lithography Group at Intel, responsible for all tool development in the area of OPC, rigorous lithography simulation, double patterning, and inverse lithography. Vivek also represents Intel on several DFM forums, and is currently Chair of the SPIE DFM Conference.